Design And Implementation of a Compact 32-Bit RISC V Core Using  Hybrid Adders

Vinod Metta; Vaishali Pande; Arvind Padole; Pratik Dhote; Harvansh Katre

Design And Implementation of a Compact 32-Bit RISC V Core Using Hybrid Adders

Author(s)	Vinod Metta, Vaishali Pande, Arvind Padole, Pratik Dhote, Harvansh Katre
Country	India
Abstract	This paper presents a novel hybrid multiply accumulate unit for 32 bit ReducedInstruction Set Core processors that combines carry save adder (CSA) and carrylookahead adder (CLA) techniques. The proposed architecture optimizes three criticalmetrics are speed, power consumption, and area utilization. The design uses carrysave adders to efficiently compress partial products during multiplication withoutsequential carry propagation, minimizing power wasting signal transitions. For finaladdition, carry lookahead adders provide fast parallel carry resolution. Addition andsubtraction operations directly employ carry lookahead techniques for quick signalpropagation. The system was designed in Verilog Hardware Descriptive Language(HDL) and synthesized on Artix-7 Field Programmable Gate Array using Vivado2024. Synthesis results demonstrate 5.3 nanosecond delay and 189 MHz frequency,achieving performance equivalent to Wallace tree multipliers while consuming 18.4%fewer logic resources and 6.4% less power. Compared to conventional arraymultipliers, the design achieves 61.9% improvement in power delay product. The architecture utilizes only 1.22% of available Field Programmable Gate Arrayresources, enabling seamless integration into larger embedded systems. Functionalverification through simulation confirms correct execution of all arithmetic operationsaddition, subtraction, multiplication, and bitwise logic within a single clock cycle.The single cycle execution combined with minimal resource footprint and superiorenergy efficiency makes this design ideal for Internet of Things (IoT) devices, edgeomputing platforms, and embedded signal processing applications requiringrestricted power budgets and compact implementations.
Keywords	RISC V Architecture, Verilog, Multiply Accumulate Logic, Carry Save Adder, Carry Lookahead Adder.
Published In	Volume 7, Issue 3, May-June 2026
Published On	2026-05-22

View / Download PDF File

E-ISSN 3048-7641

doi

CrossRef DOI is assigned to each research paper published in our journal.

AIJFR DOI prefix is
10.63363/aijfr

Downloads

Research Paper Format Copyright Permission Form and Undertaking Form Cover Page Vol 7 Isu 2 Cover Page Vol 7 Isu 1 Cover Page Vol 6 Isu 6

All research papers published on this website are licensed under Creative Commons Attribution-ShareAlike 4.0 International License, and all rights belong to their respective authors/researchers.

CC-BY-SA

About AIJFR Fees & Payment Current Issue Publication Archive	Submit Research Paper Track Submission Status Publication Guidelines Publication Ethics Peer Review & Plagiarism	Join as a Reviewer Editors & Reviewers Reviewer Referral Program Get Reviewer Membership Certi.	Website/Journal Policies Usage Policy Content Policies Privacy Policy

Contact Us		+91-9898-79-39-59	editor@aijfr.com

Advanced International Journal for Research

A Widely Indexed Open Access Peer Reviewed Multidisciplinary Bi-monthly Scholarly International Journal

Design And Implementation of a Compact 32-Bit RISC V Core Using Hybrid Adders

Share this