Development of a Low Cost Lightweight Pipelined RV32IM Processor for Edge AI Processing

Author(s)	Mekala N, Sunil M. P.
Country	India
Abstract	This paper discusses the development of a lightweight 32-bit pipelined processor implementing the RISC-V instruction set architecture. The processor uses a 5-stage pipeline scheme that provides hazard detection and data forwarding. To address the needs of the computational-intensive processing, the design uses a more advanced version of the standard RV32I instruction set with built-in multiplication–accumulation operation in the ALU complemented by lightweight SIMD computations and ReLU operation. The processor is modeled in Verilog HDL code and verified on the Xilinx Artix-7 FPGA board. Results of synthesis show that the design requires only 1.5% of LUTs and less than 1% of registers. The design is clocked by 100 MHz clock generator and all timing requirements are satisfied with 3.661 ns of slack. Energy consumption simulation shows on-chip power consumption of about 0.075 W. Simulation confirms proper operation of arithmetic and memory instructions, as well as MAC operation. The proposed architecture achieves a balance between performance, efficiency, and computational capability, making it suitable for embedded and edge-AI applications.
Keywords	RISC-V, RV32IM, Pipeline Processor, FPGA, Low Power Design
Field	Engineering
Published In	Volume 7, Issue 4, July-August 2026
Published On	2026-07-17
DOI	https://doi.org/10.63363/aijfr.2026.v07i04.6867

About AIJFR Fees & Payment Current Issue Publication Archive	Submit Research Paper Track Submission Status Publication Guidelines Publication Ethics Peer Review & Plagiarism	Join as a Reviewer Editors & Reviewers Reviewer Referral Program Get Reviewer Membership Certi.	Website/Journal Policies Usage Policy Content Policies Privacy Policy

Contact Us		+91-9898-79-39-59	editor@aijfr.com

Advanced International Journal for Research