Advanced International Journal for Research

E-ISSN: 3048-7641   •   Impact Factor: 9.11

A Widely Indexed Open Access Peer Reviewed Multidisciplinary Bi-monthly Scholarly International Journal

Call for Paper Volume 6, Issue 6 (November-December 2025) Submit your research before last 3 days of December to publish your research paper in the issue of November-December.
Submit Research Paper Join as a Reviewer

Plagiarism is checked by the leading plagiarism checker TurnItIn

Call for Paper

Volume 6 Issue 6
November-December 2025

Submit your research paper

Indexing Partners
Academia Advanced Sciences Index Bielefeld Academic Search Engine CiteSeer DRJI Google Scholar Independent Search Engine & Directory Network ISI (International Scientific Indexing) Issuu Mendeley Research Networks
RefSeek ResearcherId - Thomson Reuters ResearchGate Scirus Scribd Semantic Scholar UTeM - Universiti Teknikal Malaysia Melaka Wiki for Call for Papers WorldCat Zenodo

Development of a Digital Multi-band Audio Equalizer Using Verilog

Author(s) Miss. Janhavi Sanjay Pradhan, Prof. K. S. INGLE
Country India
Abstract This paper presents the design and implementation of a digital multi-band audio equalizer using Verilog Hardware Description Language (HDL), targeting Field-Programmable Gate Array (FPGA) platforms. The work addresses the increasing demand for high-performance, real-time audio signal processing systems. Traditional analog equalizers are characterized by limitations such as low precision, phase nonlinearity, and susceptibility to distortion. The proposed system leverages digital signal processing (DSP) techniques to overcome these issues, offering superior performance and reproducibility. The core of the equalizer is a bank of Infinite Impulse Response (IIR) biquad filters, which are selected for their computational efficiency. A significant contribution of this research is the optimization of the filter's core arithmetic unit by integrating a high-speed Wallace Tree multiplier architecture. This approach is intended to minimize computational latency and improve overall system throughput. The system architecture, design methodology, and Verilog implementation details are presented. The performance of the design is analyzed based on key metrics, including frequency response, Signal-to-Noise Ratio (SNR), hardware resource utilization, and timing performance. The simulation results demonstrate the design's ability to provide precise control over audio frequency bands while maintaining high signal integrity and computational speed, validating its suitability for real-time DSP applications.
Keywords Digital Audio Equalizer, Verilog, FPGA, Digital Signal Processing, IIR Filter, Wallace Tree Multiplier.
Field Engineering
Published In Volume 6, Issue 5, September-October 2025
Published On 2025-09-27
DOI https://doi.org/10.63363/aijfr.2025.v06i05.1435
Short DOI https://doi.org/g95hw4
View / Download PDF File

Share this



E-ISSN 3048-7641
CrossRef

CrossRef DOI is assigned to each research paper published in our journal.

AIJFR DOI prefix is
10.63363/aijfr

Downloads
Research Paper Format Copyright Permission Form and Undertaking Form

All research papers published on this website are licensed under Creative Commons Attribution-ShareAlike 4.0 International License, and all rights belong to their respective authors/researchers.

CC-BY-SA Open Access

About AIJFR
Fees & Payment
Current Issue
Publication Archive 		Submit Research Paper
Track Submission Status
Publication Guidelines
Publication Ethics
Peer Review & Plagiarism 		Join as a Reviewer
Editors & Reviewers
Reviewer Referral Program
Get Reviewer Membership Certi. 		Website/Journal Policies
Usage Policy
Content Policies
Privacy Policy
Contact Us +91-9898-79-39-59 editor@aijfr.com