Power Quality Improvement in Diode Clamped Multilevel Inverter

Author(s)	Dr. Rashmy Deepak, Ms. Vijayalaxmi Mahantappa Singatalur, Ms. Likitha G Basavaraju
Country	India
Abstract	Multilevel inverters, particularly diode-clamped topologies, have emerged as effective solutions for enhancing power quality in modern power systems, including renewable energy integration and grid-connected applications. This paper investigates the performance of a 7-level diode-clampedmultilevel inverter (DCMLI) for power quality improvement, focusing on harmonic reduction and voltage waveform enhancement through advanced pulse width modulation (PWM) techniques. A comprehensive simulation study using MATLAB/Simulink evaluates Sinusoidal PWM (SPWM) withvarious carrier disposition schemes. Results demonstrate that Modified SVPWM with Phase Disposition (PD) and trapezoidal carriers achieves the lowest Total Harmonic Distortion (THD) of 7.35% for phase voltage, alongside 15–16% improved DC link utilization compared to conventional SPWM. Experimental validation on a 400 V prototype confirms these findings, with THD reduced to 7.98%
Keywords	Power Quality, Diode-Clamped Multilevel Inverter, Sinusoidal PWM, Switching Losses, Multi-level Topology, Voltage Balancing
Field	Engineering
Published In	Volume 7, Issue 3, May-June 2026
Published On	2026-06-06

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